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Schematic Capture

Overview

LayCIR  is a flexible and powerful full-function multi-level schematic capture environment developed particularly to enable IC circuit design engineers to enter schematics accurately, clearly and quickly. In addition it has the integrated ability to support cross-probing between schematic and layout views using the network extracted.

LayCIR includes many powerful features including the availability of an unlimited hierarchy which can be navigated directly from the design entry window with a single command. It offers a rich selection of digital and analog net-list formats and is intimately linked to LaySIM and other simulation environments allowing such advanced features as back-annotation and voltage probing from simulation results.

Coupled with LayED, LayCIR provides a schematic or net-list driven layout mode in which the layout implementation is monitored using the schematic or net-list.

LayCIR has evolved as an advanced form of the program SPE, also developed by TexEDA Design Inc.. Many enhancements and additional features have been added. Nevertheless SPE is still available.

LayCIR has two distinct modes of data entry.One uses the same form of entry as SPE, namely select the command and then the item to be addressed. A more flexible form in which items are selected before the command is issued is now also available. LayCIR is fully compatible with LayFRAME, whereas SPE must be used as a point solution application.

Highlights

• Optional entry modes
• Enables rapid entry of complex schematics
• Is built around comprehensive editing features
• Provides easy navigation of design hierarchy
• Allows calculation and display of device and symbol parameters
• Generates net-lists in various digital and analog formats
• Closely coupled with LaySIM simulation tools
• Enables schematic-driven layout or net-list-driven layout
• Allows cross-probing with LayED layout

Feature Details

• Graphical data may be created and edited as a hierarchical set of schematic drawings
• Data is stored in ASCII format allowing conversion to standard or non-standard formats
• Edit flexibility includes copying between windows, and intra-window dragging
• Data elements include symbols, attributes, texts, wires, buses, bus taps, and pins (for wires and buses)
• Unlimited bus widths
• Deep “undo” stack (default set at 50)
• No limit on design size or complexity
• Unlimited number of sheets in multiple sheet drawings
• Unlimited depth of design hierarchy
• Navigation of the design hierarchy is unrestricted and traversed from the design entry window
• Symbols for both primitive and sub-circuits can be auto-generated or customized
• Auto-generated symbols have no port count limit
• Symbols are characterized using user-defined attributes which may be calculated from other attributes
• Schematics and symbols may be organized in an unlimited number of reference directories
• Flexibility is provided for the naming format of nets and buses
• Standard net-list output formats are provided (device and gate level – including HSpice, PSpice, Verilog, and VHDL).
• Hierarchical integrity checks may be carried out (schematic ERC)
• Cross-probing between LayCIR and LayED may use the same system or different systems (“socket” connection)
• Schematic-driven layout (SDLE) possible when used with LayEd (SDLE is a LayEd option)

Simulator interfaces (option)

• Intimately coupled with the LaySIM simulators
• Interfaces with certain other simulators available on the market (MSIM, Agilent ADS, and SIMetrix)