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MPW Reticle Assembly
Foundries often define specific restrictions for such parameters as die size when inviting customers to use their Multi Project Wafer (MPW) route to silicon. The advantages of such an approach when prototyping advanced and innovative circuits is clear. However, the circuit density of reticles is often low because the assembly of a number of die of different dimensions is complex. Some foundries will define a limited set of reticle sizes, for example, and this will either restrict the amount of data the customer can prototype or lead to much unused silicon area.
LayMPW offers the foundries, and companies which may wish to submit multiple die for a single process run, to optimize MPW silicon area. By using novel architectural algorithms, die size restrictions can be a thing of the past. Any number of die of unrestricted dimension may be defined and placed with a separation of a defined amount (say 100um). The program runs from a file which defines a set of parameters for each different design that is to be placed. These include an instance name, a customer reference, a technology reference, the circuit identifier, the number of die needed after sawing, the die dimensions, whether the die may be rotated, and pre-placement information in case this is required. Some die may be tagged as not required to be sawn (test inserts for process parameter checks, for example).
The program provides a layout of the completed reticle that can be viewed directly from the tool which establishes an appropriate default viewing environment (layer colors, etc.).
An example of a reticle layout view is illustrated below: