Home → LayTOOLS Support →
LayTOOLS verification run-decks to check layout databases against foundry rules (drc) and against circuit net-lists (lvs) are available from matricus for a range of technology nodes and foundries. Run-decks to extract circuit devices and parasitic devices (lpe) are also offered. The run-decks have been written and tested by professionals who understand the technology and the sophistication of the LayVER command structure. They offer, therefore, optimum checking times while ensuring complete check coverage and comprehensive violation reporting. User-definable run-time switches may be used to disable certain features (antenna checks, coverage checks, latch-up checks, etc.) are included in drc decks. Parasitic extraction decks present area (vertical), fringe, and coupling (lateral) capacitance elements while options allow disabling of default contact and via resistance extraction and metal track resistance extraction.
Foundry-specific data is protected by providing the run-files in an encrypted form which is automatically decrypted, given an appropriate license, by LayVER. Licenses are only provided on notification from the specific foundry that appropriate agreements have been exchanged.
A Verification run-deck development service is offered for technologies not presently covered.
Example of information generated as part of a LayVER drc run