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SMASH

The key software for an analog electrical designer is a simulator. With present-day technologies, however, there are certain characteristics that are vital such a tool must demonstrate. It must fully support and maintain the latest device models, it should allow composite analog and digital net-lists to run ('gates' and transistors in the same net-list), it should converge quickly and satisfactorily, and it should be able to provide straightforward approaches to analysis of such aspects as jitter and power consumption. Further, it should be closely integrated with the schematic capture tool so that compatible net-lists are generated directly and so that back-annotation of simulation parameters can be displayed on the schematic.

As silicon geometries shrink, device models become more complex and the number of elements that must be included in any simulation increases. A respected simulator must accommodate such advances as well as provide the features and options to allow effective circuit development to be completed.

This page describes the same software kernel that powers LaySIM-TEX products - software that is also made available as a stand-alone product by matricus inc.. The stand-alone version is called SMASH. It is configured in a number of standard versions as shown in the table below in order that the most cost-effective solution can be available to the user.

SMASH is an analog mixed-signal, multi-language, multi-level, single-kernel simulator. Thus it:
  • allows device definition in primitive devices or as high level descriptions
  • handles analog and discrete level signals
  • recognizes a range of net-list languages from SPICE to high level description languages
  • allows single net-lists to recognize a variety of the different languages (electrical, structural, functional, and behavioral, analog model)
  • synchronizes analog and digital partitions without delay, instability, or distortion


The result is fast, accurate, mixed signal simulations.

key features:

  • identical availability on Windows or Linux, allowing heterogeneous networking
  • the only genuine mixed-signal, multi-level, multi-domain simulator on the market today
  • supports all device-level and RTL design languages: Spice, ABCD, C, VHDL, Verilog-HDL, VHDL-AMS, Verilog-A, Verilog-AMS
  • most extensive transistor models support, including BSIM3v3 and level 49, EKV, BSIM4, VBIC, and MEXTRAM
  • SMASH-exclusive capabilities such as dynamic ERC and dynamic SRC (Electrical Rule Checks and Specification Rule Checks)
  • a rich range of utilities including SLED for schematic capture and RTL flow-charting, as well as COACH to interface with Cadence Composer

additional features:

  • STI stress equations for BSIM3/ BSIM4 family of models including both Berkeley and TSMC specific equations
  • enhanced DSP toolbox for periodic signal characterization with jitter measurement and histograms
  • streamlined transient noise analysis, taking into account custom equations and noise parameters
  • batch-mode data-extraction on FFT results
  • Verilog-AMS small signal analysis
  • analog operators in Verilog-AMS such as transition filters, slew integrators and circular integrators
  • enhancement of time control for Verilog timing checks and VHDL VITAL

Options

Discovery†

AMS

Trio

Mecha

LMS/Verilog

LMS/VHDL

All-in-one

 graphical entry

 

 

Heart of SMASH

mixed signal kernel

graphic interface

batch interface

advanced waveform viewer

unlimited circuit size

 

six operating point heuristics

four analog solvers

Languages

SPICE

 

Verilog-HDL structural

 

 

Verilog-HDL behavioral

 

 

 

Verilog-A

 

 

 

Verilog-AMS

 

 

 

 

VJDL

 

 

VHDL-AMS

 

 

 

C/System C

 

ABCD

 

PSL

 

 

Features

ASIC device-level models*

 

Relax

 

VHDL VITAL

 

 

Verilog SDF

 

 

Advanced Features

dynamic ERC

 

Hi-Z net detection

 

transient noise

 

phase noise

 

imbalance location

 

sensitivity location

 

jitter simulation

 

GUITAR**

equivalence checking

HDL code coverage

 

integrated HDL debugger

 

waveform expression editor

 

†Discovery                       node and functionality-limited software for initial evaluation

*ASIC models include:      BSIM3, BSIM4, PSP, EKV, ACM, MM9, VBIC, MEXTRAM

**GUITAR                        Graphic User Interface for Trading Accuracy and Rapidity

 SMASH developer information:

        Information on the software developer, Dolphin Integration, and other Dolphin products may be found at:

 
Dolphin Logo

http://www.dolphin-integration.com/

 

 

 
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