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LaySIM-TEX products LaySIM-A and LaySIM-LMS integrate a comprehensive industry standard simulator which can boast a history that goes back over thirty years and a product that was first launched to the market almost a quarter a century ago. That product was in fact the first ever seamless, mixed signal, single-engine simulator available on the market. Since that early start, Verilog_HDL superseded the originally implemented logic simulator, which was then supplemented with an option implementing the Verilog-A standard. Later VHDL and VHDL-AMS were added as options as those standards emerged. Many additional features were added during this evolution including jitter tolerance assessment, dynamic and static power consumption assessment, and transient noise simulation. The product is now an industry standard, single-kernel, mixed-mode EDA tool used by many design houses as their standard simulator. LaySIM-TEX is powered by this powerful SMASH kernel developed by Dolphin.

LaySIM-TEX has been integrated into the LayTOOLS software and provides the user with a robust and reliable simulator, rich in features, that reduces set-up time and provides fast accurate execution.The product is shipped from natricus, and is fully integrated with other LayTOOLS applications. matricus also distributes the native SMASH products for users who do not use LayTOOLS.

The two basic LaySIM-TEX options offered by matricus are:

a basic analog version (LaySIM-A for those users working with small mixed signal designs where no digital hardware description modeling is required
an advanced mixed mode version (LaySIM-LMS) for those users wishing integrate analog simulation with digital and analog modeling


The following table summarizes the characteristics included in these offerings:






Heart of LaySIM

All-in-one mixed signal kernel

Graphic interface (GUI)

Graphic waveform viewer

Unlimited circuit size

Five operating point heuristics

Four analog solvers






Verilog AMS



Basic Features

Rich set of device models*



Advanced Features

Dynamic ERC

Hi-Z net insertion

Transient noise

Phase noise

Imbalance location

Sensitivity location

Jitter simulation


Equivalence checking

HDL code coverage


Integrated HDL debugger


Waveform expression editor


Operating point


Small signal

DC transfer


fast Fourier transform

Monte Carlo



Operating Systems

Windows XP, Vista, 7 (32, 64 bit)

Linux x86

*    Simulation models include BSIM3, BSIM4, PSP, EKV, ACM, MM9, VBIC, and MEXTRAM

**  GUITAR is a graphics user interface to optimize simulation (accuracy against run-time)



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